Next generation Nb superconductor integrated circuit process

We have developed our next generation Nb integrated circuit process which o ffers higher performance, particularly for SFQ-type logic, and increased de nsity compared to our present 2000 A/cm(2) foundry process. The new process is based on our existing Nb founds process, but has been optimized to util ize more of the sub-micron alignment and exposure capabilities of our optic al lithography tools. Minimum linepitch and junction size have been reduced to 2.5 mu m (from 4 mu m) and 1.75 mu m (from 2.5 mu m), respectively, and J(c) has been increased to 4000 A/cm(2). These goals have been achieved by an overall reduction in layer thicknesses, implementation of SF6 dry etch for metal line definition, and optimization of the photolithography process . The new process offers lower inductance wiring and substantially lower pa rasitic circuit inductances compared with the existing Nb foundry process. In this paper, we discuss these improvements and report parametric test dat a for devices fabricated in this process.