Speed, integration scale, and production cost of digital electronics are al
l constrained by circuit yield. This Is true in any technology. In Josephso
n circuits, parameter variations figure prominently into the yield equation
. Extensive statistical data exist for processes such as TRW's Nb and NbN t
echnologies; yield calculation is a way to relate these data to circuit per
formance. To determine parametric yield using Monte Carlo, any and all circ
uit parameters are treated as Gaussian random variables. This kind of yield
calculation has now been incorporated into the MALT optimization utility [
1]. As a worked example, we analyze a stacked SQUID amplifier design. The t
echnique reveals circuit dynamics that are difficult to uncover by other me
ans.