High-frequency clock operation of Josephson 256-word x 16-bit RAMs

Citation
S. Nagasawa et al., High-frequency clock operation of Josephson 256-word x 16-bit RAMs, IEEE APPL S, 9(2), 1999, pp. 3708-3713
Citations number
10
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science
Journal title
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
ISSN journal
10518223 → ACNP
Volume
9
Issue
2
Year of publication
1999
Part
3
Pages
3708 - 3713
Database
ISI
SICI code
1051-8223(199906)9:2<3708:HCOOJ2>2.0.ZU;2-0
Abstract
A Josephson 256-word x 16-bit RAM that includes a power circuit has been de veloped to enable high-frequency clock operation. This RAM consists of a 4 x 4 matrix array of 256RAM blocks, impedance-matched lines, and signal ampl ifiers. A power-supply circuit, composed of a transformer and a Josephson r egulator, is included in each 256RAM block Fail bit maps for the 256RAM blo ck were measured, and perfect operation with a 100% bit yield was obtained. The 256RAM block functioned up to a clock frequency of 1.07 GHz. We succee ded in feeding a large high-frequency current of more than 2 A into the ent ire 256-word x 16-bit RAM. The 256-word x 16-bit RAM therefore functioned u p to a clock frequency of 620 MHz.