Simulation and 18 Gb/s testing of a data-driven self-timed RSFQ demultiplexer

We have developed a Data Driven Self-Timed (DDST) Rapid-Single-Flux-Quantum (RSFQ) demultiplexer (demux) for the interface between on-chip high-speed RSFQ circuits and off-chip low-speed circuits. In order to eliminate the ti ming issue in a synchronous clocking system we employed the DDST architectu re, where a clock signal is localized within a 2-bit basic demur module and dual rail lines are used to transfer the timing information between the mo dules. A larger demur can be produced simply by connecting the 2-bit module s in a tree structure. The DDST demur was designed for 10 Gb/s operation wi th sufficient de bias margin using HYPRES 1 kA/cm(2) Nb process. We have su ccessfully tested operation of the 2-bit demur up to 18 GHz using the DDST on-chip high-speed test system which was developed in our group.