Efficiency of chip-level versus external power combining

In this paper, we compare two S-band high-efficiency switched-mode amplifie rs designed around two commercially available packaged MESFET's, one having a four times larger gate periphery than the other. The amplifiers using th e larger and smaller devices are designed to operate in classes E and F, re spectively. The smaller device gives 685-mW output power with 7.4-dB gain a nd 64% overall efficiency. The larger device gives 1.70-W output power with 5.3-dB gain and 57% overall efficiency. This gives an internal (or chip-le vel) power-combining efficiency for the larger device of 89% in terms of ov erall efficiency. This is compared to the combining efficiency of circuit a nd spatial power combining using high-efficiency amplifiers, with the goal of assessing which architecture is the most efficient in terms of total dis sipated power (dc and RF).