Analysis of the impact of proximity correction algorithms on circuit performance

Variation in channel length degrades circuit reliability and yield. A commo n way to compensate for this problem is to increase the mean channel length , which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the lin e width is influenced by local layout patterns. It is possible to compensat e for this effect by resizing transistor gates appropriately on the mask. H owever, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correc tion scheme with limited resources, we have developed a method to compare d ifferent correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor, In particular, to evaluate correction algorithms while avoiding the high co st associated with generating multiple mask sets and fabricating product wa fers with each of these mask sets, we present a method for predicting the c orrection results using simulation. Our methodology involves a DRC-based ap proach for gate resizing, along with critical path simulation for evaluatin g circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical te st results were used to calibrate the device models for circuit simulation.