AN EFFICIENT PIPELINED PARALLEL ARCHITECTURE FOR BLOCKING EFFECT REMOVAL IN HDTV

This paper presents an efficient architecture for blocking effect remo val in HDTV. Since there is a lot of image signal for signal processin g in digital HDTV, the memory size and the fast operation have been th e main concerns of the DSP(Digital Signal Processing) architectures. T o reduce the size of a memory, a memory is partitioned into many memor y banks. This makes it possible to access the memory concurrently. Als o, to improve the operation speed, a pipelined parallel architecture a nd a memory scheduling technique are adopted. Since multiplications an d divisions are time-critical, these operations are replaced with shif tings. Therefore this architecture is very fast and uses small size me mory banks, and this makes it possible to realize a real-time signal p rocessor.