The Godfather CPLD architecture

Vantis consider that their new complex programmable logic device (CPLD) arc hitecture, code-named Godfather, addresses user needs for higher integratio n, time to market, and speed performance. Initial devices will be based on a 4 metal EE CMOS technology using a 0.25 mu m effective length (L-eff) and provide densities up to 1,024 macrocells. Key aspects are an innovative hi erarchical interconnect structure and logic blocks and macrocells which hav e been enhanced with respect to previous architectures. The architecture an d the resulting performance are discussed.