Architecture for fault diagnosis of CMOS ICs with BIC based I-DDQ testing

Authors
Segura, J Isern, E Roca, M
Citation
J. Segura et al., Architecture for fault diagnosis of CMOS ICs with BIC based I-DDQ testing, ELECTR LETT, 35(14), 1999, pp. 1152-1153
Citations number
3
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
35
Issue
14
Year of publication
1999
Pages
1152 - 1153
Database
ISI
SICI code
0013-5194(19990708)35:14<1152:AFFDOC>2.0.ZU;2-D
Abstract
An architecture for simplifying fault diagnosis is presented. The method is applied to circuits incorporating built-in current (BIC) sensors and is ba sed on hardware partitioning, does not increase the number of pins and is i ndependent of the fault diagnosis heuristic at the logic level.