SCHEDULING FOR IC SORT AND TEST FACILITIES WITH PRECEDENCE CONSTRAINTS VIA LAGRANGIAN-RELAXATION

This paper presents an effective scheduling algorithm for an integrate d circuit (IC) test floor environment where wafer sort and final test are performed. Two particular features of scheduling IC test floor fac ilities are incorporated in this study: (1) Each job requires more tha n one resource to be used simultaneously to process the job. The const raints on each individual resource have to be dealt with. (2) Each job needs to be processed through a number of operations with different t emperatures in a specific order. Therefore, strict precedence constrai nts on these operations have to be considered. In this paper, the sche duling problem for IC test floor facilities is modeled as an integer, programming problem and is solved using the Lagrangian relaxation tech nique. Comparisons of results with those obtained from other heuristic dispatching rules are also given.