New self-aligned processes for III-V electronic high speed devices

We report on two new self-aligned processes intended for microelectronic de vices realization exhibiting a significant reduction of the number of eleme ntary technological levels. These processes allow to obtain a very short se lf-aligned contact separation without using spacers or wet etched mesa over hangs. As an example, only three lithographic masks are used to realize a t riple mesa self-aligned heterojunction bipolar transistor (HBT). A bilayer resist process is used to define the specific shape of the upper contact th at is used for self-alignment. A combination of selective, isotropic, or an isotropic processes and very simple selective lift-off processes are used t o define the mesa and the contacts which are also used as masks during etch ing. The alloying of contacts may be performed just after deposition and li ft-off. These processes can reduce the production cost and increase the rel iability for integration in comparison with conventional self-alignment usi ng the selective wet etched emitter overhang in the HBT application. Furthe rmore, the parasitic access resistance can be reduced both by using thin me sa active layers and decreasing the contacts separation. This separation le ngth can be determined by the aspect ratio of the bilayer resist, the chara cteristics, and parameters of the contact deposition equipment. At last, lo w induced damage inductively coupled plasma dry etch processes are partly u sed to reduce the dry etch damages. (C) 1999 American Vacuum Society. [S073 4-211X(99)06104-1].