A 40-gb/s integrated clock and data recovery circuit in a 50-GHz f(T) silicon bipolar technology

Clock and data recovery (CDR) circuits are key electronic components in fut ure optical broadband communication systems. In this paper, we present a 40 -Gb/s integrated CDR circuit applying a phase-locked loop technique. The IC has been fabricated in a 50-GHz f(T) self-aligned double-polysilicon bipol ar technology using only production-like process steps. The achieved data r ate is a record value for silicon and comparable with the best results for this type of circuit realized in Sice and III-V technologies.