Decomposition and technology mapping of speed-independent circuits using Boolean relations

This paper presents a new technique for decomposition and technology mappin g of speed-independent circuits. An initial circuit implementation is obtai ned in the form of a netlist of complex gates, which may not be available i n the design library, The proposed method iteratively performs Boolean deco mposition of each such gate F into a two-input combinational or sequential gate G available in the library and two gates H-1 and H-2 simpler than F, w hile preserving the original behavior and speed-independence of the circuit . To extract functions for H-1 and H-2 the method uses Boolean relations as opposed to the less powerful algebraic factorization approach used in prev ious methods, After logic decomposition, the overall library matching and o ptimization is carried out. Logic resynthesis, performed after speed-indepe ndent signal insertion for H-1 and H-2, allows for sharing of decomposed lo gic. Overall, this method is more general than the existing techniques base d on restricted decomposition architectures, and thereby leads to better re sults in technology mapping.