On wirelength estimations for row-based placement

Wirelength estimation in very large scale integration layout is fundamental to any predetailed routing estimate of timing or routability. In this pape r, we develop efficient wirelength estimation techniques appropriate for wi relength estimation during top-down floorplanning and placement of cell-bas ed designs. Our methods give accurate, linear-time approaches, typically wi th sublinear time complexity for dynamic updating of estimates (e.g,, for a nnealing placement). Our techniques offer advantages not only for early on- line wirelength estimation during top down placement, but also for a poster iori estimation of routed wirelength given a final placement. In developing these new estimators, we have made several contributions, including 1) ins ight into the contrast between region-based and bounding box-based rectilin ear Steiner minimal tree (RStMT) estimation techniques; 2) empirical assess ment of the correlations between pin placements of a multipin net that is c ontained in a block; and 3) new wirelength estimates that are functions of a block's complexity (number of cell instances) and aspect ratio.