An integrated logical and physical design flow for deep submicron circuits

This paper presents a set of techniques and a new design how to be used in the synthesis of high-performance deep-submicron logic circuits. The design flow consists of circuit partitioning into tree-like clusters, floorplanni ng, global routing, and timing analysis/budgeting steps, followed by simult aneous technology mapping and linear placement of each cluster. The strengt h of this approach lies in the dynamic programming-based algorithms used in performing simultaneous technology mapping and linear placement of the log ic clusters. The two algorithms me propose, one for exact total (gate plus routing) area minimization and the other for total (gate plus routing) dela y minimization, generate a set of noninferior solutions for each cluster en abling designers to perform tradeoffs between total-area and total-delay. E xperimental results on large benchmarks prove the effectiveness of the prop osed how.