Slicing floorplans with boundary constraints

Citation
Fy. Young et al., Slicing floorplans with boundary constraints, IEEE COMP A, 18(9), 1999, pp. 1385-1389
Citations number
12
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN journal
02780070 → ACNP
Volume
18
Issue
9
Year of publication
1999
Pages
1385 - 1389
Database
ISI
SICI code
0278-0070(199909)18:9<1385:SFWBC>2.0.ZU;2-Q
Abstract
In floorplanning of very large scale integration design, it is useful if us ers are allowed to specify some placement constraints in the packing. One p articular kind of placement constraints is to pack some modules on one of t he four sides: on the left, on the right, at the bottom, or at the top of t he final floorplan, These are called boundary constraints. In this paper, w e enhanced a well-known slicing floorplan algorithm [10] to handle these bo undary constraints. Our main contribution is a necessary and sufficient cha racterization of the Polish expression, a representation of the intermediat e solutions in the simulated annealing process, so that we can check these constraints efficiently and can fis the expression in case the constraints are violated. We tested our algorithm on some benchmark data and the perfor mance is good.