Multiple branch prediction for wide-issue superscalar

Modern micro-architectures employ superscalar techniques to enhance system performance. Since the superscalar microprocessors must fetch at least one instruction cache line at a time to support high issue rate and large amoun t speculative executions. There are cases that multiple branches are often encountered in one cycle. And in practical implementation this would cause serious problem while there are variable number of instruction addresses th at look up the Branch Target Buffer simultaneously. In this paper, we propo se a Range Associative Branch Target Buffer (RABTB) that can recognize and predict multiple branches in the same instruction cache line for a wide-iss ue micro-architecture. Several configurations of the RABTB are simulated an d compared using the SPECint95 benchmarks. We show that with a reasonable s ize of prediction scope, branch prediction can be improved by supporting mu ltiple / up to 8 branch predictions in one cache line in one cycle. Our sim ulation results show that the optimal RABTB should be 2048 entry, 8-column range-associate and 8-entry modified ring buffer architecture using PAs pre diction algorithm. It has an average 5.2 IPC_f and branch penalty per branc h of 0.54 cycles. This is almost two times better than a mechanism that mak es prediction only on the first encountered branch.