The use of Silicon Carbide semi-insulating wafers has to be mastered in ord
er to reach output power densities up to 3-4 W mm(-1) in the 1-2 GHz freque
ncy range (values that are currently targeted). This study shows that the b
uffer layer doping level and thickness have a great influence on the MESFET
behavior. We have studied three epilayer configuration on SI substrates th
at differ only by the buffer layer. On two of them, a slow drain current de
crease in d.c. mode was observed. On the third one, no d.c. current drift w
as observed without rf input power, but drain current decreases instantaneo
usly when rf input power is switched on. Traps, located either in the buffe
r layer or in the substrate are supposed to be responsible for these drift
phenomena. Load-pull measurements were performed at 2 GHz on transistors fa
bricated on the three different structures. One of them, with a 2 mm gate p
eriphery, has been measured under 72 V drain-source bias voltage and 2.1 W
mm(-1) power density was obtained at 2 GHz. We believe these results are th
e first to be published on a SIC MESFET with d.c. bias voltage over 70 V. (
C) 1999 Elsevier Science S.A. All rights reserved.