Balanced compensation for highly linear MOSFET gate capacitor branch

Authors
Leeavattananon, K Toumazou, C Hughes, JB
Citation
K. Leeavattananon et al., Balanced compensation for highly linear MOSFET gate capacitor branch, ELECTR LETT, 35(17), 1999, pp. 1409-1410
Citations number
5
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
35
Issue
17
Year of publication
1999
Pages
1409 - 1410
Database
ISI
SICI code
0013-5194(19990819)35:17<1409:BCFHLM>2.0.ZU;2-8
Abstract
The compatibility of the switched-capacitor technique with standard digital CMOS processes utilising MOSFET gate capacitance has recently been investi gated. Owing to its high voltage-dependence, a technique for enhancing line arity which is suitable for non-delay-free circuits is proposed. The techni que was verified by simulation to demonstrate its effectiveness for lineari ty improvement.