Flip chip (FC) packaging is gaining acceptance in the electronics packaging
arena. here sources of bumped die and high density printed wiring boards (
PWB's) laminates become available every day. Also, known good die (KGD) iss
ues are being resolved by several companies, and design tools to perform FC
packaging designs are becoming more available, This is the infrastructure
FC packaging requires to become the packaging method of choice, particularl
y for >200 I/O applications. FC packages come in a variety of styles: FC pl
astic ball grid arrays (FC/PBGA's), FC plastic quad Bat packs (FC/PQFP's),
etc. Presently, the industry's drive is toward single chip packages on low
cost laminates; i.e., organic substrates. Work is starting to occur in the
area of multichip FC packages, due to the need to increase memory to microp
rocessor speed communication. In this article, a unique FC/MCM-L package wi
ll be discussed. Part I will concentrate on the development and reliability
testing of a one to four chip leadless FC/MCM-L package. Unlike traditiona
l surface mount (SM) components that are attached to printed wiring boards
(PWB's) with leads, the SM pads within the body of the package are used for
attachment to a PWB. Collapsible eutectic solder domes are deposited on th
e SM pads by traditional screen printing. After reflow, these domes are use
d to connect the FC/MCM-L to the PWB. Challenges encountered during package
design, PWB fabrication and first and second level assembly will be discus
sed, Part II of this article will focus on the extension of this FC/MCM-L p
ackage to a EGA second level interconnect, Change of FC attachment method,
design enhancements, assembly, and reliability testing results will be pres
ented.