Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform

In this paper, we present architectures and scheduling algorithms for encod ers and decoders that are based on the two-dimensional discrete wavelet tra nsform, We consider the design of encoders and decoders individually, as we ll as in an integrated encoder-decoder system. We propose architectures ran ging from a single-instruction multiple-data processor arrays to folded arc hitectures that are suitable for single-chip implementations, The schedulin g algorithms for the folded architectures range from those that try to mini mize the latency to those that try to minimize the storage and keep the dat a flow regular. We include a comparison of the performance of these algorit hms to aid the designer in choosing one that is best suited for a specific application.