Reconfigurable pipelined 2-D convolvers for fast digital signal processing

In order to make software applications simpler to write and easier to maint ain, a software digital signal-processing library that performs essential s ignal- and image-processing functions is an important part of every digital signal processor (DSP) developer's toolset. In general, such a library pro vides high-level interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work. Complex si gnal transformations then become function calls, e.g., C-callable functions . Considering the two-dimensional (2-D) convolver function as an example of great significance for DSP's, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initial ly configured by software programming. Therefore, the exploration of the 2- D convolver's design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors. Based on the specific c onvolver, and considering operators supported in the library as hardware ac celerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed, In terms of implementation, this paper explores the performance and architectural trade offs involved in the design of an FPGA-based 2-D convolution coprocessor fo r the TMS320C40 DSP microprocessor available from Texas Instruments Incorpo rated, Dallas, TX, However, the proposed concept is not limited to a partic ular processor.