Low-power memory mapping through reducing address bus activity

Arrays in behavioral specifications that are too large to fit into on-chip registers are usually mapped to off-chip memories during behavioral synthes is, We address the problem of system power reduction through transition cou nt minimization on the memory address bus when these arrays are accessed fr om memory. We exploit regularity and spatial locality in the memory accesse s and determine the mapping of behavioral array references to physical memo ry locations to minimize address bus transitions. We describe array mapping strategies for two important memory configurations: all behavioral arrays mapped to a single off-chip memory and arrays mapped into multiple memory m odules drawn from a library. For the single memory configuration, we descri be a heuristic for selecting a memory mapping scheme to achieve low power f or each behavioral array. For mapping into a library of multiple memory mod ules, we formulate the problem as three logical-to-physical memory mapping subtasks and present experiments demonstrating the transition count reducti ons based on our approach. Our experiments on several image processing benc hmarks show power savings of up to 63%, through reduced transition activity on the memory address bus in the single memory case. We also observe a fur ther transition count reduction by a factor of 1.5-6.7 over a straightforwa rd mapping scheme in the multiple memories configuration.