The design of a SRAM-based field-programmable gate array - Part II: Circuit design and layout

Field-programmable gate arrays (FPGA's) are now widely used for the impleme ntation of digital systems, and many commercial architectures are available . Although the literature and data books contain detailed descriptions of t hese architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I of this paper, we described the high-leve l architectural design of a static random-access memory programmable FPGA, This paper will address the circuit-design issues through to the physical l ayout. We address area-speed tradeoffs hi the design of the logic block cir cuits and in the connections between the logic and the routing structure. A ll commercial FPGA designs are done using full-custom hand layout to obtain absolute minimum die sizes. This is both labor and time intensive, We prop ose a design style with a minitile that contains a portion of all the compo nents in the logic tile, resulting in less full-custom effort. Thtr minitil e is replicated in a 4 x 4 array to create a macro tile. The minitile is op timized for layout density and speed, and is customized in the array by add ing appropriate vias, This technique al;so permits easy changing of the har d-wired connections in the logic block architecture and the segmentation le ngth distribution in the routing architecture.