A memory-based architecture for MPEG2 system protocol LSI's

This paper proposes a memory-based architecture implementing the MPEG2 syst em protocol large scale integrations (LSI's), and demonstrates its flexibil ity and performance. The memory-based architecture implements the full func tionality of the MPEG2 system protocol for both multiplexing and demultiple xing MPEG2-encoded streams. It consists of a core central processing unit, memories, and dedicated application-specific hardware. It is designed and o ptimized by hardware/software codesign techniques. The LSI's provide suffic ient performance and flexibility for real-time application of the MPEG2 sys tem protocol, They were fabricated with 0.5-mu m complimentary metal-oxide semiconductor embedded gate array process technology. They are now in use o n MPEG2 CODEC systems for several multimedia communication and storage serv ices.