A proposal for a standard procedure for moderately accelerated electromigration tests on metal lines

This work is aimed at proposing a standard procedure for moderately acceler ated Electromigration (EM) tests applied to interconnection lines of the pr esent and the next future generation of integrated circuits. The procedure has been tested on one metal level test structures using an AI-alloy metall ization scheme, but can be easily applied to other materials as well as to metal lines with vias. Different existing standards have been taken into co nsideration to define this proposal: ASTM F1260-89, JEDEC JESD33-A, JESSI A C41. In the PROPHECY project, the focus was on wafer level reliability eval uation with fast methods, but fast EM methods using extremely accelerated s tress conditions usually induce side-effects which can invalidate the resul ts. As a consequence, this procedure suggests the use of moderately acceler ated tests, together with a method for reducing the number of tests needed for a complete EM characterization. This procedure gives advice on the test structures to be used and on the preliminary steps to be performed before the EM tests. A measurement system, complying with the requirements of this procedure, is also briefly described. The methods described in this docume nt apply to both package- and wafer-level measurements. In order to validat e this procedure, EM tests have been performed on JESSI AC41 specimens. (C) 1999 Elsevier Science Ltd. All rights reserved.