Wafer level backside emission microscopy: sample preparation

Emission microscopy has been widely adopted as an important tool for analyz ing integrated circuit failures from the front surface. More recently, the development of multi-level metallization, flip-chip and lead-on-chip packag e designs either eliminated or greatly restricted this inspection avenue. A n obvious alternative is to inspect from the backside of semiconductors. Ho wever, as silicon itself is a light-blocking material. thinning the back su rface becomes essential to successful backside emission microscopy (EM). Th is paper describes a thinning and polishing technique enabling a user to lo cally thin a defective die on a wafer, This local thinning and polishing al lows the wafer to retain its overall mechanical strength to survive the sub sequent microprobing while providing a viewing window for EM analysis throu gh the backside. (C) 1999 Elsevier Science Ltd. All rights reserved.