Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance

Authors
Citation
Yx. Gao et Df. Wong, Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance, INTEGRATION, 27(2), 1999, pp. 165-178
Citations number
12
Categorie Soggetti
Computer Science & Engineering
Journal title
INTEGRATION-THE VLSI JOURNAL
ISSN journal
01679260 → ACNP
Volume
27
Issue
2
Year of publication
1999
Pages
165 - 178
Database
ISI
SICI code
0167-9260(199907)27:2<165:SAVWTM>2.0.ZU;2-S
Abstract
In this paper, by using calculus of variations, we determine the optimal sh ape for a wire under the Elmore delay model. Coupling capacitance has been taken into consideration explicitly by treating it as another source of gro unded capacitance. Given two wires in parallel, one has uniform width and t he other has non-uniform width whose shape is described by a function f(x). Let T-D, be the delay through the non-uniform wire. We determine f(x) such that T-D, is minimized, We also extend our study to the case where a non-u niform wire has two neighboring wires. Our study shows that the optimal sha pe function satisfies an integral equation. Numerical methods are employed to solve the corresponding differential equation and carry out the integrat ion. We provide an efficient algorithm to find the optimal solution. Experi ments show that it only takes several iterations to get the optimal results by using our algorithm, Our experiments also show that the wire delay T-D, is a convex function of the wire width at the driver end. (C) 1999 Elsevie r Science B.V. All rights reserved.