Low temperature unhydrogenated in-situ doped polysilicon thin film tra
nsistors with a SiO2 deposited gate insulator were fabricated using a
four-mask aluminium gate process. Several processes were varied-in par
ticular the deposition pressure of the polysilicon layers, thermal ann
ealing, and cleaning process of the surface of the active layer. The t
wo polysilicon layers, which make up the active layer and the in-situ
doped source and drain regions, were deposited at an optimized pressur
e (P=90 Pa) in the amorphous state and crystallized by a thermal annea
ling. This procedure was performed before plasma etching of the source
/drain polysilicon layer. An oxygen plasma + RCA-type wet cleaning wer
e used to ensure the obtainment of a good APCVD SiO2 gate insulator/ac
tive layer interface quality. Therefore, these thin film transistors e
xhibit good electrical properties:a low threshold voltage (approximate
to 2V), a high field effect mobility (>60 cm(2)Vs(-1)), and a high On
/Off state current ratio (greater than or equal to 10(7)) for a drain
voltage V-ds = 1 V. It is worth noting that these results are similar
to those of hydrogenated TFTs made using this type of process. Consequ
ently the TFTs described here could be good candidates for flat panel
display applications. (C) 1997 Elsevier Science S.A.