A flexible and expendable neuroimage processor architecture

An analog versatile neuroimage processor (VNIP) architecture is proposed he re. VNIP can process various types of neural network and image processing s tructures, without any hardware modification. The structure allows unlimite d expansion of network size and the compensation of process variation. The proof-of-concept chip is implemented, using a combination of continuous-tim e multiplier and switched-capacitor techniques. The throughput is 12 x 10(6 ) synapses/s . mm(2) and the energy consumption is 10(-9) J/synapse. A test chip was fabricated, using a 1.2-mu m double-poly CMOS process and tested, verifying the flexibility and expandability of the architecture.