High-efficiency harmonic loaded oscillator with low bias using a nonlineardesign approach

We present a design method for an optimized high-efficiency harmonic loaded oscillator, The proposed approach predicts the performance of oscillators including output power, dc-RF conversion efficiency, and de-bias current sh ift during start-up transition. In this method, the performance of the osci llator can be optimized based on the performance analysis of the active dev ice under the assumed operation conditions, The effects of fundamental and harmonic loading on output power and efficiency are investigated by the pro posed approach. Two kinds of stability conditions are addressed for an osci llator initially biased at a low gate voltage, Using the proposed approach, we design an oscillator that has a high efficiency of 61 % at 1.86 GHz wit h a very low bias voltage of 2.0 V.