On the performance and limitations of a dual threshold discriminator pixelreadout circuit for LHC

The analog front-end of pixel readout electronics with dual threshold discr iminator scheme has been measured extensively to determine the optimum perf ormance and performance Limitations of the circuit. The preamplifier shows a peaking time of 20ns without capacitive load, which degrades to only 30ns with a load of 350fF. The LEVEL-discriminator has an adjustable threshold in the range of 2000 to 6000e(-) with a variable separation to the TIME-dis criminator threshold of 800 to 1600e(-), The circuit allows the full suppre ssion of out-of-time signals under the conditions of 350fF capacitive load and a total power consumption of 40 mu W per cell. The untuned threshold di spersion is measured to be 320e(-) r.m.s., which reduces to 70e(-) r.m.s. a fter threshold adjust. The overall noise of the circuit reaches a value of about 200e(-) r.m.s. with 350fF capacitive load and 20nA of parallel curren t at the preamplifier input. Further measurements characterize the time-ove r-threshold (TOT) behaviour and the double-pulse resolution of the circuit.