LOW-TEMPERATURE GROWTH AND RELIABILITY OF FERROELECTRIC MEMORY CELL INTEGRATED ON SI WITH CONDUCTING BARRIER STACK

Citation
Am. Dhote et al., LOW-TEMPERATURE GROWTH AND RELIABILITY OF FERROELECTRIC MEMORY CELL INTEGRATED ON SI WITH CONDUCTING BARRIER STACK, Journal of materials research, 12(6), 1997, pp. 1589-1594
Citations number
26
Categorie Soggetti
Material Science
ISSN journal
08842914
Volume
12
Issue
6
Year of publication
1997
Pages
1589 - 1594
Database
ISI
SICI code
0884-2914(1997)12:6<1589:LGAROF>2.0.ZU;2-E
Abstract
Polycrystalline LSCO/PNZT/LSCO ferroelectric capacitor heterostructure s were grown by pulsed laser deposition using a composite conducting b arrier layer of Pt/TiN on poly Si/Si substrate, The growth of the ferr oelectric heterostructure is accomplished at a temperature in the rang e of 500-600 degrees C, This integration results in a 3-dimensional st acked capacitor-transistor geometry which is important for high densit y nonvolatile memory (HDNVM) applications, Transmission electron micro scopy shows smooth substrate-film and film-film interfaces without any perceptible interdiffusion, The ferroelectric properties and reliabil ity of these integrated capacitors were studied extensively at room te mperature and 100 degrees C for different growth temperatures. The cap acitors exhibit excellent reliability, both at room temperature and at elevated temperatures, making them very desirable for HDNVM applicati ons.