We present the design and the test performed on ADeLinel, a Full-Custom Ana
log Memory for sparse data sampling. It has been designed as an array of sw
itched capacitors. It is only one channel of 8 cells. The control part of t
he ADeLine chip is custom designed for the size reduction, high speed perfo
rmance and low power dissipation. The memory has been integrated in double
poly, double metal AMS 0.8 mu m CMOS. It has 3.5 V input and output swings,
a linearity within +/- 6 mV in a 2 V range and 11 bits of resolution. (C)
1999 Elsevier Science B.V. All rights reserved.