Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations

Device characteristics and reliability in a 3.3-V logic CMOS technology wit h Various gate oxidation and nitridation processes are described. The techn ology was designed to extend 3.3-V devices to the ultimate dielectric relia bility limit while maintaining strict manufacturing cost control. A nitride d gate oxide provided the means to maintain hot-electron reliability at the level of the previous iteration, but at higher performance and fewer proce ssing cost. Conventional furnace processes in nitrous and nitric oxide, hig h-pressure oxidation in oxygen and nitrous oxide, and rapid-thermal process es using nitrous and nitric oxide were investigated. We found that the conc omitant variations in fixed charge and thermal budget have a significant in fluence on both n-FET and p-FET device parameters such as threshold voltage , carrier mobility, and inverse short-channel effect (ISCE). Reliability ef fects, such as charge to breakdown (Q(BD)), hot-electron degradation, and n egative-bias temperature instability (NBTI) were examined and correlated wi th the nitrogen profile in the gate dielectric. Secondary ion mass spectros copy (SIMS) profiles were used to characterize the oxidation techniques and to correlate gate dielectric composition to the parametric and reliability parameters.