Key measurements of ultrathin gate dielectric reliability and in-line monitoring

High-performance CMOS products depend upon the reliability of ultrathin gat e dielectrics. In this paper a methodology for measuring thin gate dielectr ic reliability is discussed in which the focus is upon the elements of thos e test structures used in the evaluation, the design of the reliability str ess matrix, and the generation of engineering design models. Experimental r esults are presented which demonstrate the reliability of ultrathin gate di electrics measured on a wide variety of test structures with dielectric thi cknesses ranging from 7 to 3.5 nm, An overview is provided for thin gate ox ide reliability that was measured on integrated functional chips-high-perfo rmance microprocessors and static random-access memory (SRAM) chips. The da ta from these measurements spanned the period from early process and device development to full production. Manufacturing in-line monitoring for thin gate dielectric yield and reliability is also discussed, with several case histories presented which show the effectiveness of monitors in detecting p rocess-induced dielectric failures. Finally, causes of oxide fails are disc ussed, leading to the process actions necessary for controlling thin gate d ielectric defects.