Average-case technology mapping of asynchronous burst-mode circuits

This paper presents a technology mapper that optimizes the average performa nce of asynchronous burst-mode control circuits. More specifically, the map per can be directed to minimize either the average latency or the average c ycle time of the circuit. The input to the mapper is a burst-mode specifica tion and its NAND-decomposed unmapped network, The mapper preprocesses the circuit's specification using stochastic techniques to determine the relati ve frequency of occurrence of each state transition. Then, it maps the NAND -decomposed network using a given library of gates. Of many possible mappin gs, the mapper selects a solution that minimizes the sum of the delays (lat ency or cycle time) of all state transitions, weighted by their relative fr equencies, thereby optimizing for average performance. We present experimen tal results on a large set of benchmark circuits, which demonstrate that ou r mapped circuits have significantly lower average latency and cycle time t han comparable circuits mapped with a leading conventional mapping techniqu e which minimizes the worst case delay. Moreover, these performance improve ments can be achieved with manageable run-times and significantly smaller a rea.