Fault emulation: A new methodology for fault grading

In this paper, we introduce a method that uses the held programmable gate a rray (FPGA)-based emulation system for fault grading. The real-time simulat ion capability of a hardware emulator could significantly improve the perfo rmance of fault grading, which is one of the most time-consuming tasks in t he circuit design and test process. We employ a serial fault emulation algo rithm enhanced by two speed-up techniques. First, a set of independent faul ts can be injected and emulated at the same time. Second, multiple dependen t faults can be simultaneously injected within a single FPGA-configuration by adding extra circuitry. Because the reconfiguration time of mapping the numerous faulty circuits into the FPGA's is pure overhead and could be the bottleneck of the entire process, using extra circuitry for injecting a lar ge number of faults can reduce the number of FPGA-reconfigurations and, thu s, improving the performance significantly. In addition, we address the iss ue of handling potentially detected faults in this hardware emulation envir onment by using the dual-railed logic. The performance estimation shows tha t this approach could be several orders of magnitude faster than the existi ng software approaches for large sequential designs.