Three-dimensional versus two-dimensional finite element modeling of flip-chip packages

Authors
Citation
Q. Yao et J. Qu, Three-dimensional versus two-dimensional finite element modeling of flip-chip packages, J ELEC PACK, 121(3), 1999, pp. 196-201
Citations number
13
Categorie Soggetti
Mechanical Engineering
Journal title
JOURNAL OF ELECTRONIC PACKAGING
ISSN journal
10437398 → ACNP
Volume
121
Issue
3
Year of publication
1999
Pages
196 - 201
Database
ISI
SICI code
1043-7398(199909)121:3<196:TVTFEM>2.0.ZU;2-T
Abstract
In this study, both two-dimensional and three-dimensional finite element an alyses were used to study the stress distribution in and deflection of the flip chip assembly under thermal loading. It is found that the three-dimens ional results compared favorably with experimental measurements, while the two-dimensional results consistently overestimate both stresses and deflect ion. Among the two-dimensional models, the plane stress assumption seems to yield results closer to the full three-dimensional predictions. Furthermor e, three-dimensional models were used to ;investigate the effect of printed wiring board size on the overall deflection of the flip-chip assembly. Thi s size effect of the printed wiring board has significant implications on t he design of multi-chip modules. The results indicate that a square array p lacement pattern is preferable to a staggered array for multiple chip modul es in order to reduce mechanical interaction between chips. For square arra ys, such mechanical interaction between chips can be neglected when the min imum distance between adjacent chips is more than 2 times the chip size.