Jh. Song et al., Design and characterization of a 10 Gb/s clock and data recovery circuit implemented with phase-locked loop, ETRI J, 21(3), 1999, pp. 1-5
A clock and data recovery circuit with a phase-locked Loop for 10 Gb/s opti
cal transmission system was realized in a hybrid IC form. The quadri-correl
ation architecture is used for frequency- and phase-locked loop. A NRZ-to-P
RZ converter and a 360 degree analogue phase shifter are included in the ci
rcuit. The jitter characteristics satisfy the recommendations of ITU-T The
capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were sh
owed. The temperature compensation characteristics were tested for the oper
ating temperature from -10 to 60 degrees C and showed no increase of error,
This circuit was adopted for the 10 Gb/s transmission system through a nor
mal single-mode fiber with the length of 400 km and operated successfully.