A new tapered TEOS oxide technique has been developed to use field oxide of
the power integrated circuits. It pro,ides better uniformity of less than
3 % and reproducibility, On-resistance of P-channel RESURF (REduced SURface
Field) LDMOS transistors has been optimized and improved by using a novel
simulation and tapered TEOS field oxide on the drift region of the devices.
With the similar breakdown voltage, at V-gs= -5.0 V, the specific on-resis
tance of the LDMOS with the tapered field oxide is about 31.5 m Omega.cm(2)
, while that of the LDMOS with the conventional field oxide is about 57 m O
mega.cm(2) .