A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)(2)) latch and its application in a dual-modulus prescaler

A high-speed dual-phase dynamic-pseudo NMOS ((DP)(2)) latch using clocked p seudo NMOS inverters is presented. Compared to the conventional D-latch, th is circuit has a higher maximum operating frequency and consumes lower dyna mic power at a given operating frequency, The latch has been demonstrated b y utilizing it in the synchronous counter section of a dual-phase dual-modu lus prescaler implemented in a 0.8-mu m CMOS process. The maximum operating frequency for the prescaler at 3 V supply voltage is 1.3 GHz, while the po wer consumption is 9.7 mW, This power consumption is significantly lower th an those of the previously reported prescalers implemented in 0.8-mu m CMOS processes. The 9.7-mW power consumption at 1.3 GHz also compares favorably to the 24-mW power consumption of the 1.75-GHz prescaler using MOS current mode latches implemented in a 0.7-mu m CMOS process, A 25% reduction of th e maximum operating frequency for a similar to 60% reduction of the power c onsumption should be a useful tradeoff.