A new compact physics-based alpha-power law MOSFET model is introduced to e
nable projections of low power circuit performance for future generations o
f technology by linking the simple mathematical expressions of the original
alpha-power law model with their physical origins. The new model, verified
by HSPICE simulations and measured data, includes: 1) a subthreshold regio
n of operation for evaluating the on/off current tradeoff that becomes a do
minant low power design issue as technology scales, 2) the effects of verti
cal and lateral high field mobility degradation and velocity saturation, an
d 3) threshold voltage roll-off. Model projections for MOSFET CV/I indicate
a 2X-performance opportunity compared to the National Technology Roadmap f
or Semiconductors (NTRS) extrapolations for the 250, 180, and 150 nm genera
tions subject to maximum leakage current estimates of the roadmap, NTRS and
model calculations converge at the 70 nm technology generation, which exhi
bits pronounced on/off current interdependence for low power gigascale inte
gration.