A chip-multiprocessor architecture with speculative multithreading

Much emphasis is now placed on chip-multiprocessor (CMP) architectures for exploiting thread-level parallelism in an application. In such architecture s, speculation may be employed to execute applications that cannot be paral lelized statically. In this paper, we present an efficient CMP architecture for speculative execution of sequential binaries without source recompilat ion. We present the software support that enables identification of threads from a sequential binary. The hardware includes a memory disambiguation me chanism that enables the detection of interthread memory dependence violati ons during speculative execution. This hardware is different from past prop osals in that it does not rely on a snoopy-based cache-coherence protocol. Instead, it uses an approach similar to a directory-based scheme. Furthermo re, the architecture includes a simple and efficient hardware mechanism to enable register-level communication between on-chip processors. Evaluation of this software-hardware approach shows that it is quite effective in achi eving high performance when running sequential binaries.