An effective built-in self-test scheme for parallel multipliers

In this paper, an effective Built-in Self-Test (BIST) scheme for parallel m ultipliers (array and tree) is proposed. The new scheme combines the advant ages of deterministic and pseudorandom testing and avoids their drawbacks. No modifications to the multiplier structure are required. A guaranteed ver y high fault coverage of a comprehensive cellular fault model is achieved. The results do not depend either on the gate-level implementation of the mu ltiplier cells or the architecture of the multiplier (carry-propagate or ca rry-save array multiplier or tree multiplier) or on the multiplier size. A small deterministic test set of highly regular test vectors is used which e xploits the inherent regularity of the multiplier architecture. The regular ity of the test vectors allows for their on-chip generation with very small hardware overhead equivalent to the hardware overhead of pseudorandom test ing.