A cost-efficient and fully-pipelinable architecture for DCT/IDCT

Authors
Hsiao, SF Shiue, WR Tseng, JM
Citation
Sf. Hsiao et al., A cost-efficient and fully-pipelinable architecture for DCT/IDCT, IEEE CONS E, 45(3), 1999, pp. 515-525
Citations number
15
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
ISSN journal
00983063 → ACNP
Volume
45
Issue
3
Year of publication
1999
Pages
515 - 525
Database
ISI
SICI code
0098-3063(199908)45:3<515:ACAFAF>2.0.ZU;2-L
Abstract
A novel low-cost and low-power linear array for computation of discrete cos ine transform (DCT) and its inverse is derived from the heterogeneous depen dence graphs representing the factorized coefficient matrices. Due to the n ovel algorithm and the corresponding efficient architectural design, the ne w DCT/IDCT processor is easily pipelined and the power consumption can be r educed significantly by turning off the operation of arithmetic units whene ver possible.