Fully-parallel VLSI implementation of vector quantization processor using neuron-MOS technology

An analog vector quantization processor has been designed based on the neur on-MOS (vMOS) technology. In order to achieve a high integrating density, t emplate information is merged into the matching cell (the absolute value ci rcuitry) using the vMOS ROM. technology. A new-architecture vMOS winner-tak e-all (WTA) circuit is employed for fully-parallel search for the minimum-d istance vector. The WTA performs multi-resolution winner search with an aut omatic feedback gain control. A test chip having 256 16-element fixed templ ate vectors has been built in a 1.5-mu m double-polysilicon CMOS technology with the chip size of 7.2 mm x 7.2 mm, and the basic operation of the circ uits has been demonstrated.