IC implementation of a switched-current chaotic neuron

Citation
R. Herrera et al., IC implementation of a switched-current chaotic neuron, IEICE T FUN, E82A(9), 1999, pp. 1776-1782
Citations number
25
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
ISSN journal
09168508 → ACNP
Volume
E82A
Issue
9
Year of publication
1999
Pages
1776 - 1782
Database
ISI
SICI code
0916-8508(199909)E82A:9<1776:IIOASC>2.0.ZU;2-O
Abstract
A switched-current integrated circuit, which realizes the chaotic neuron mo del, is presented. The circuit mainly consists of CMOS inverters that are u sed as transconductance amplifiers and nonlinear elements. The chip was fab ricated using a 1.2 mu m HP CMOS process. A single neuron cell occupies onl y 0.0076 mm(2), which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequenc y of 2 MHz.