A scalable pipelined memory architecture for fast ATM packet switching

This paper describes the design of a scalable pipelined memory buffer for a shared scalable buffer ATM switch. The memory architecture provides high s peed and scalability, and eliminates the restriction of memory cycle time i n a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. The architecture consists of a 2- D array configuration of small memory banks. Increasing the array configura tion enlarges the entire memory capacity. Maximum cycle time of a designed scalable memory is 4ns. The designed memory is embedded in the prototype ch ip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160- bit SRAM memory banks. It is integrated in 0.6 mu m double-metal single-pol y CMOS technology.