Easily testable realization based on single-rail-input OR-AND-EXOR expressions

It is known that AND-EXOR two-level networks obtained by AND-EXOR expressio ns with positive literals are easily testable. They are based on the single -rail-input logic, and require (n + 4) tests to detect their single stuck-a t faults, where n is the number of the input variables. We present three-le vel networks obtained from single-rail-input OR-AND-EXOR expressions and pr opose a more easily testable realization than the AND-EXOR networks. The re alization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1 less than or e qual to r less than or equal to n). We show that only (r + n/r) tests are r equired to detect the single stuck-at faults by adding r extra variables to the network.